1. Technical Field
The embodiment described herein relates to a semiconductor integrated circuit (IC) and, more particularly, to a delay locked loop (DLL) circuit included in a semiconductor IC.
2. Related Art
A conventional semiconductor IC, such as an apparatus functioning as synchronous dynamic random access memory (SDRAM), has increased operational speed as a result of its use of clock signals. Such a semiconductor IC includes a clock buffer to buffer an external input clock signal. In some cases, the semiconductor IC uses a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit to generate for itself an internal clock signal with which the phase difference between the internal and the external clock signals is corrected. In the internal clock signal used in the semiconductor IC, the ratio of the time within a cycle in which a voltage is at “high” level and the time in which the voltage is at a “low” level interval, i.e., the “duty ratio,” is typically set at 50:50. However, such semiconductor ICs often include numerous delay elements, as this can cause the duty ratio of the internal clock signal to vary.
Due to the high-speed operation of many present semiconductor ICs, the utilization of clock signals has increased, and thus, a clock signal having a relatively stable duty ratio is more critical. Accordingly, DLL circuits in semiconductor ICs have been built to include duty cycle correction units to stabilize the duty ratios of clock signals. The technology to correct duty cycles has become increasingly important for utilizing stable clock signals during the high speed operation of the semiconductor ICs.
DLL circuitry has been designed to correct the duty cycle of a reference clock signal that has been input into a delay line by imparting duty cycle correction functionality to a clock input buffer that generates the reference clock signal by buffering an external clock signal. Such DLL circuitry includes a duty cycle control unit for detecting the duty cycle of the reference clock signal and for controlling the duty cycle correction operation of the clock input buffer. The duty cycle control unit increases or decreases the high level interval of the reference clock cycle by adjusting the voltage level supplied to the clock input buffer.
However, although the duty ratio of the reference clock signal output from the clock input buffer is improved by the above-described operation, the toggle timing frequency of the reference clock signal changes. This phenomenon occurs because the rising edge and the falling edge of the reference clock signal are not fixed during the duty cycle correction operation of the clock input buffer. As a result, when the toggle timing of the reference clock signal varies, the amount of delay of the clock input buffer, which is modeled by a replica delayer, and the amount of the actual delay are different from each other, Thus, the precision deteriorates in the delay locking of the DLL circuit. As described above, although the DLL circuit has implemented technology to correct the duty cycle, the toggle timing frequency of the reference clock signal varies and reliability of the clock delay locking operation, a primary operation of the DLL circuit, deteriorates.